1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method and circuit for repairing a nonvolatile ferroelectric memory device that enables a user to control a redundancy operation of the memory device in accordance with an encrypted condition.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FeRAM), becomes the center of attention as the next-generation memory device since it has a data processing speed of the dynamic random access memory (DRAM) grade and preserves stored data even if the power is off.
The FeRAM is a memory device having a similar structure to the DRAM, and uses a high residual dielectric polarization that is the characteristic of a ferroelectric material that is used as a material of a capacitor in the memory device.
Due to the characteristic of the residual dielectric polarization, the data stored in the memory device is not erased even if an applied electric field is removed.
FIG. 1 is a characteristic diagram illustrating the hysteresis loop of a general ferroelectric material.
As shown in FIG. 1, even though the electric field is removed, the polarization induced by the electric field does not vanish due to the existence of the residual dielectric polarization (or spontaneous polarization), but is kept a specified amount (i.e., states d and a).
In the nonvolatile ferroelectric memory cell, the states d and a can correspond to 1 and 0, respectively, and this characteristic enables the cell to be used as a memory device.
Hereinafter, the conventional nonvolatile ferroelectric memory device will be explained with reference to the accompanying drawings.
FIG. 2 is a view illustrating the construction of a unit cell of the conventional nonvolatile ferroelectric memory device.
As shown in FIG. 2, the unit cell of the conventional nonvolatile ferroelectric memory cell includes a bit line B/L formed in one direction, a word line W/L formed in a direction crossing the bit line B/L, a plate line P/L formed in the same direction as the word line W/L at a specified distance from the word line W/L, a transistor T whose gate is connected to the word line W/L and whose source is connected to the bit line B/L, and a ferroelectric capacitor FC whose first terminal is connected to a drain of the transistor T and whose second terminal is connected to the plate line P/L.
The conventional method of repairing a nonvolatile ferroelectric memory device will now be explained with reference to the accompanying drawings.
FIG. 3 is a view illustrating the conventional rapair algorithm of a nonvolatile ferroelectric memory device.
As illustrated in FIG. 3, after the whole process is completed, a chip test is performed through proceeding of a full address memory test (3a) and a fail address analysis step (3b) for finding a fail address.
Then, if it is possible to relieve the fail address as analyzed above by a relieving circuit, a relief fuse block performs a fuse cutting in the form of a fuse capable of coding the corresponding address using a laser beam (3c).
If the corresponding fail address is inputted after completion of the fuse cutting, an active signal is generated from the relieving circuit to activate the relief cell.
Meanwhile, a main cell corresponding to the address is inactivated by an inactive signal of the relieving circuit.
Accordingly, the main cell of the corresponding fail address is inactivated, and the relief cell is activated.
However, the conventional method of repairing a nonvolatile ferroelectric memory device as described above has the following problems.
First, since the fuse cutting is performed using the laser, the repair becomes impossible if the fail is produced after a packaging process, and this causes the fail to be increased to deteriorate the quality of a product.
Second, since expensive laser equipment should be provided, the manufacturing cost of the device is increased.